The von Neumann architecture
The von Neumann architecture, which is also known as the von Neumann model and Princeton architecture, is a computer architecture based on that described in 1945 by the mathematician and physicist John von Neumann and others in the First Draft of a Report on the EDVAC. This describes a design architecture for an electronic digital computer with parts consisting of a processing unit containing an arithmetic logic unit and processor registers. a control unit containing an instruction register and program counter. a memory to store both data and instructions; external mass storage and input and output mechanisms. The meaning has evolved to be any stored-program computer in which an instruction fetch and a data operation cannot occur at the same time because they share a common bus. This is referred to as the von Neumann bottleneck and often limits the performance of the system.
The design of a von Neumann architecture machine is simpler than that of a Harvard architecture machine, which is also a stored-program system but has one dedicated set of address and data buses for reading data from and writing data to memory, and another set of address and data buses for fetching instructions.
The processing unit can be broken down into a coupe of sub units, the ALU, the processing control unit and the program counter. The ALU compute the arithmetic logic needed to run programs (adding and subtracting to registers etc.) To be simple, the control unit just controls the flow of data through the processor. It could be called the brain of the processor if you will. The program essentially points to when you are in instruction memory, it keeps track of what instruction you are running at the moment and increments when done.